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(Solved): Problem 1. A) Write A Behavioral Model Of J-K Flip-flop With Active-low Asynchronous Reset. B) Write...

Problem 1.

a) Write a behavioral model of J-K flip-flop with active-low asynchronous reset.

b) Write a proper test-bench and stimulus, thoroughly test your J-K-FlipFlop. Also, show your waveform and describe why your JK-FF does what is is designed to do.

Problem 2.

a) Write a Verilog module that will assert its output if a 4-bit input binary word is even.

b) Show the waveform for two input patterns “1100” and “0101”

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Expert Answer

answer1 a.) an async. reset mean the reset/ clear can occur even when there is no posedge of clock at the time an active low keword mean that the rest value for activation will be 0 instead of 1 modul
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