(Solved): Problem 1. A) Write A Behavioral Model Of J-K Flip-flop With Active-low Asynchronous Reset. B) Write...
a) Write a behavioral model of J-K flip-flop with active-low asynchronous reset.
b) Write a proper test-bench and stimulus, thoroughly test your J-K-FlipFlop. Also, show your waveform and describe why your JK-FF does what is is designed to do.
a) Write a Verilog module that will assert its output if a 4-bit input binary word is even.
b) Show the waveform for two input patterns â€œ1100â€ and â€œ0101â€